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Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
FEATURES
* Dual device * Low threshold voltage * Fast switching * Logic level compatible * Surface mount package
PHN210
SYMBOL
d1 d1 d2 d2
QUICK REFERENCE DATA
VDS = 30 V ID = 3.4 A RDS(ON) 100 m (VGS = 10 V) RDS(ON) 200 m (VGS = 4.5 V)
s1 g1 s2 g2
GENERAL DESCRIPTION
Dual N-channel enhancement mode field-effect transistor in a plastic envelope using 'trench' technology. Applications:* Motor and relay drivers * d.c. to d.c. converters * Logic level translator The PHN210 is supplied in the SOT96-1 (SO8) surface mounting package.
PINNING
PIN 1 2 3 4 5,6 7,8 DESCRIPTION source 1 gate 1 source 2 gate 2 drain 2 drain 1
SOT96-1
8 7 6 5
pin 1 index
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Repetitive peak drain-source voltage Continuous drain-source voltage Drain-gate voltage Gate-source voltage Drain current per MOSFET1 Drain current per MOSFET (both MOSFETs conducting)1 Drain current per MOSFET (pulse peak value) Total power dissipation (either or both MOSFETs conducting)1 Storage & operating temperature CONDITIONS Tj = 25 C to 150C RGS = 20 k Ta = 25 C Ta = 70 C Ta = 25 C Ta = 70 C Ta = 25 C Ta = 25 C Ta = 70 C MIN. - 65 MAX. 30 30 30 20 3.4 2.8 2.4 1.9 14 2 1.3 150 UNIT V V V V A A A A A W W C
1 Surface mounted on FR4 board, t 10 sec February 1999 1 Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted, FR4 board, t 10 sec Surface mounted, FR4 board TYP. 150
PHN210
MAX. 62.5 -
UNIT K/W K/W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy (per MOSFET) Non-repetitive avalanche current (per MOSFET) CONDITIONS Unclamped inductive load, IAS = 3.4 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 15 V; RGS = 50 ; VGS = 10 V MIN. MAX. 13 3.4 UNIT mJ A
ELECTRICAL CHARACTERISTICS
Tj= 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs ID(ON) IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 10 A; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 2.2 A VGS = 4.5 V; ID = 1 A VGS = 10 V; ID = 2.2 A; Tj = 150C Forward transconductance VDS = 20 V; ID = 2.2 A On-state drain current VGS = 10 V; VDS = 1 V; VGS = 4.5 V; VDS = 5 V Zero gate voltage drain VDS = 24 V; VGS = 0 V; current VDS = 24 V; VGS = 0 V; Tj = 150C Gate source leakage current VGS = 20 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 2.3 A; VDD = 15 V; VGS = 10 V MIN. 30 27 1 0.4 2 3.5 2 TYP. MAX. UNIT 2 80 120 4.5 10 0.6 10 6 0.7 0.7 6 8 21 15 2.5 5 250 88 54 2.8 3.2 100 200 170 100 10 100 V V V V V m m m S A A nA A nA nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 20 V; RD = 18 ; VGS = 10 V; RG = 6 Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source diode current (per MOSFET) Pulsed source diode current (per MOSFET) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 C MIN. IF = 1.25 A; VGS = 0 V IF = 1.25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V -
PHN210
TYP. MAX. UNIT 0.82 69 55 2.2 14 1.2 A A V ns nC
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
100 Peak Pulsed Drain Current, IDM (A) PHN210
10
RDS(on) = VDS/ ID
tp = 10 us 100 us 1 ms
1
10 ms 100 ms
0.1
10 s
0.01
0
20
40
60 80 100 Tamb / C
120
140
0.1
1 10 Drain-Source Voltage, VDS (V)
100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta)
Fig.3. Safe operating area. Ta = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
Normalised Current Derating
100 Peak Pulsed Drain Current, IDM (A) D = 0.5 10 0.2 0.1 0.05 1 0.02 P D 0.1 single pulse T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 tp D = tp/T PHN210
0
20
40 60 80 100 Ambient temperature, Tamb (C)
120
140
Pulse width, tp (s)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); conditions: VGS 10 V
Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
PHN210
6 Drain Current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain-Source Voltage, VDS (V) 1.8 2 VGS = 20 V Tj = 25 C 4.2 V 4V 3.8 V 3.6 V 3.4 V 3.2 V 2 1 0 10 V 5V 5
Transconductance, gfs (S)
Tj = 25 C 4 150 C 3
0
1
2
3
4 5 6 7 Drain current, ID (A)
8
9
10
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID) ; parameter Tj
a
0.5
Drain-Source On Resistance, RDS(on) (Ohms) 3.2 V 3.4 V 3.6 V 3.8V 4V 4.2 V Tj = 25 C
2
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
0.4
1.5
0.3
1
0.2 VGS =5 V 10V 20V 0 0 1 2 3 4 5 6 Drain Current, ID (A) 7 8 9 10
0.1
0.5
0 -50
0
50 Tj / C
100
150
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj)
VGS(TO) / V 4
Drain current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Tj = 25 C 150 C VDS > ID X RDS(ON)
3
max. typ.
2
1
min.
0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
PHN210
1E-01
Sub-Threshold Conduction
10 9
Source-Drain Diode Current, IF (A) VGS = 0 V
1E-02 min typ max
8 7 6 5 4 Tj = 25 C 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
1E-03
150 C
1E-04
1E-05
1E-06
0
1
2
3
4
5
Drain-Source Voltage, VSDS (V)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Non-repetitive Avalanche current, IAS (A) 10 PHN210
Capacitances, Ciss, Coss, Crss (pF) 1000 25 C Ciss 1 100 Coss Crss
VDS tp ID
Tj prior to avalanche =125 C
10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
0.1 1E-06
1E-05
1E-04 Avalanche time, tp (s)
1E-03
1E-02
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load
Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 2.3A Tj = 25 C VDD = 15 V
1
2
3
4 5 6 7 Gate charge, QG (nC)
8
9
10
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS
February 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PHN210
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
Fig.16. SOT96 surface mounting package.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8".
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel enhancement mode TrenchMOSTM transistor
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHN210
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
February 1999
7
Rev 1.000

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